The present invention relates to integrated circuit structures and fabrication methods.
Background: Sidewall Spacers
A technology which was first proposed in the 1970s is sidewall spacers on MOS gate structures. These sidewall spacers perform two important functions: they provide a lateral separation between the conductive gate material and conductive cladding (such as silicide) which may be present on the surface of the source/drain regions; and they also provide a useful alignment for the lightly doped drain regions. That is, a lighter dose of the source/drain dopant is preferably implanted before the sidewall spacers are in place, to form lightly-doped-drain (LDD) or medium-doped-drain (MDD) extension regions; a heavier dose is preferably implanted after the sidewall spacers are in place. This provides some self-aligned lateral separation between the most heavily doped parts of the source/drain diffusions and the corner of the gate.
During the 1990s, it has become increasingly common to fabricate such sidewall spacers using silicon nitride (Si3N4) rather than silicon dioxide. Silicon nitride has the advantage that a selective oxide etch, such as the source/drain contact etch, can stop on the nitride. Thus, it is no longer necessary to impose an offset rule between the contact location and the gate location (particularly if the top of the gate is also covered with silicon nitride). See, for example, U.S. Pat. No. 5,439,846, which is hereby incorporated by reference.
Conventionally the nitride sidewalls are deposited by a low-pressure chemical vapor deposition, or "LPCVD," process. However, this is a high-temperature process, typically performed at or above 700 degrees Centigrade, and this high temperature has become increasingly undesirable as this results in some degree of unwanted dopant diffusion. Also, since the nitride etch selectivity over SiO2 is low, a thicker oxide must be deposited over the gate to serve as an etch stop and prevent the etching of silicon.
Prior solutions to the dopant-diffusion problem have incorporated low-temperature Si3N4 depositions. However, the deposition rates of such processes are inherently low and prohibit their use in volume manufacturing.
Prior solutions to improving selectivity of Si3N4 to SiO2, in order to stop the sidewall etch before silicon is exposed, have concentrated on improvements in the etch process. To date, typical selectivities are in the 3-4 range.
Transistor and Process Structure with Silicon Carbide Sidewall Spacers
The present application describes a new process for fabricating transistors, using silicon carbide sidewall spacers. The use of silicon carbide has two distinct advantages over the conventional use of silicon nitride: first, good quality silicon carbide can be deposited at temperatures of 600 degrees C and below. Secondly, silicon carbide can be etched selectively to oxide. This is very convenient for forming the sidewall spacer, since the risk of erosion of the underlying thin oxide is reduced.
Advantages of the disclosed methods and structures include:
selectivity of etching SiC on SiO2 allows use of a thinner oxide to cap the gate, beneath the sidewall material, important for short channel length CMOS; PA1 lower deposition temperature decreases lateral diffusion of dopants, especially for PMOS devices; PA1 lower deposition temperature reduces base-width of vertical NPN's with boron of BF2 bases; PA1 reduces emitter diffusion in vertical PNP's.